Senior Scientist Digital Design RISC-V

Deine Rolle im Team

Unsere Erwartungen an dich

Qualifikationen

• Demonstrate strong proficiency in HDLs (SystemVerilog, VHDL).
• Excel in architecture exploration and micro-architecture development.
• Possess in-depth knowledge of on-chip infrastructure (AMBA/PCIe/USB/JTAG, NoC).
• Have a solid background in silicon development and digital IP design/integration.
• Exhibit proficiency in Static Timing Analysis tools and Clock Domain Crossing.
• Show expertise in functional and formal verification.
• Apply skills in scripting languages (Tcl, Python, Perl, MATLAB, Shell-scripting).
• Communicate effectively in verbal and written English; knowledge of German is an advantage.
• Software development skills (bare metal, RISC-V/ARM) are beneficial.
• Autonomous, well-organized, and thrive in a dynamic and multicultural team environment.
• Effective in strategy development is an advantage.
• Strong track record in business development and winning projects.

Erfahrung

• PhD in digital IC design with at least 3 years of relevant experience, or MSc in a relevant field with at least 5 years of relevant experience.
• Utilize experience with back-end tools (synthesis and Place & Route).
• Leverage experience with EDA tools (simulator/debug/synthesis/timing analysis/place & route) from major vendors (Synopsys, Cadence, Mentor).
• Experience with FPGA tools (e.g., Xilinx).
• Proven project management experience.
• Experience in team leadership or PhD supervision is highly desirable.